View P82C150AHT_77806.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
P82C150 CAN Serial Linked I/O device (SLIO) with digital and analog port functions
Preliminary specification Supersedes data of 1995 Oct 11 File under Integrated Circuits, IC18 1996 Jun 19
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
CONTENTS 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 8 9 10 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 12 13 13.1 13.2 13.3 13.4 14 15 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION I/O functions I/O registers CAN functions Initialization P82C150 operation after RESET or change of bus mode LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION Maximum bus length Start up sequence External oscillator mode Using digital I/O port functions Using DPM Using ADC Using analog input port functions CAN-bus system applications PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
P82C150
1996 Jun 19
2
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
1 FEATURES 2 GENERAL DESCRIPTION
P82C150
* Single-chip I/O device with CAN protocol controller * Meets CAN protocol specification version 2.0 A and B (passive) with restricted bit timing * Fully integrated clock oscillator (no crystal required) * 16 configurable digital or analog I/O port pins * Each of the port pins individually configurable via CAN-bus: port direction, port mode and event capture facilities for inputs (event driven or polling) * Up to sixteen digital inputs; automatic transmission of a CAN message on a change on inputs individually selectable * Up to sixteen 3-state outputs * Up to two quasi-analog outputs with 10-bit accuracy * 10-bit analog-to-digital converter with up to six multiplexed analog input channels (for accuracy see Section 11.6) * Two general purpose comparators * Bit rate from 20 kbit/s up to 125 kbit/s using internal oscillator * Automatic bit rate detection and calibration * Up to sixteen P82C150 nodes for one CAN-bus system * Four identifier bits programmable * SLIO functions controlled by a single intelligent node (`host') * Sleep-mode with wake-up via CAN-bus * Differential CAN-bus input comparator and CAN-bus output driver * Supply voltage: 5 V 4% * Operating temperature: two ranges -40 to +85 C and -40 to +125 C. 3 ORDERING INFORMATION
The P82C150 is a single-chip 16-bit I/O device including a Controller Area Network (CAN) protocol controller with automatic bit rate detection and calibration. It features 16 configurable I/O port pins with programmable direction, digital and analog modes. The P82C150 provides a configurable event capture facility supporting automatic transmission caused by a change on the port input pins. The clock oscillator requires no external components, thus, the cost of the CAN link is reduced significantly. The P82C150 is a very cost-effective way to increase the I/O capability of a microcontroller based CAN node as well as to reduce the amount and complexity of wiring. Advanced safety is provided by the CAN protocol. Applications: * Body electronics and instrumentation in automotive applications * Sensor/actuator interface in automotive and general industrial applications * Extension of I/O capabilities of microcontroller based CAN nodes.
PACKAGE TYPE NUMBER NAME P82C150 AFT P82C150 AHT SO28 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm
TEMPERATURE RANGE (C) VERSION SOT136-1 -40 to +85 -40 to +125
1996 Jun 19
3
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
4 BLOCK DIAGRAM
P82C150
handbook, full pagewidth
+5 V AVDD 18
+5 V VDD 8
P16 16 I/O port pins 9 to 16 P8 to P15 P5 to P7
17
RXO 21 CAN-bus RX1
bus mode OSCILLATOR clock AND CALIBRATOR
22
input comparator
5, 6, 7 PORT LOGIC
19 REF
REFERENCE VOLTAGE
1/2 AV DD BIT STREAM PROCESSOR TRANSMIT/ RECEIVE LOGIC I/O REGISTERS
1, 2, 3
P2 to P4
27, 28 P0/CLK, P1
RST
23
bus mode +
TX1 26 CAN-bus TX0 25 ERROR MANAGEMENT LOGIC
P82C150
IDENTIFIER LATCH
24 XMOD
20 AVSS
4 VSS
MHA064
Fig.1 Block diagram.
1996 Jun 19
4
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
5 FUNCTIONAL DIAGRAM
P82C150
VDD
handbook, full pagewidth
AVDD P16 ADC feedback output
RX0 CAN-bus inputs RX1
P15 reference voltage output REF P14 P13 TX1 CAN-bus outputs P11 TX0 P10 P12
analog-to-digital comparator input multiplexed analogto-digital signal analog input comparator inputs DPM1 output
P82C150
P9 P8 P7 P6 analog inputs, analog switches 16-bit digital I/O
RST (reset) P5 P4 P3 P2 XMOD P1 P0/CLK VSS AVSS
MHA066
DPM2 output
identifier programming
Fig.2 Functional diagram.
1996 Jun 19
5
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
6 6.1 PINNING INFORMATION Pinning
P82C150
handbook, halfpage
P2 P3 P4 V SS P5 P6 P7
1 2 3 4 5 6 7
28 P1 27 P0/CLK 26 TX1 25 TX0 24 XMOD 23 RST 22 RX1
P82C150
VDD 8 P8 9 21 RX0 20 AVSS 19 REF 18 AV DD 17 P16 16 P15 15 P14
MHA065
P9 10 P10 11 P11 12 P12 13 P13 14
Fig.3 Pin configuration.
1996 Jun 19
6
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
6.2 Pin description Pin description for P82C150; SO28; see note 1 DESCRIPTION I/O Ports P2 to P3; Identifier programming input. I/O Port 4; DPM2 output. Ground, digital part (0 V; logic circuits and CAN-bus driver). I/O Ports P5 to P6; analog input. I/O Port 7; analog input or analog-to-digital comparator 1 output. Power supply, digital part (+5 V; logic circuits and CAN-bus driver). I/O Port 8; analog input or comparator 3 output. I/O Port 9; analog input or comparator 2 output. I/O Port 10; comparator 3 inverting input or DPM1 output. I/O Port 11; comparator 3 non-inverting input. I/O Port 12; comparator 2 inverting input. I/O Port 13; comparator 2 non-inverting input. I/O Port 14; multiplexed analog signal. I/O Port 15; analog-to-digital comparator input. Feedback output of analog-to-digital converter. Power supply, analog part (+5 V; CAN input, oscillator and reference). Reference voltage output (12 x AVDD). Ground, analog part (0 V; CAN input, oscillator, reference). CAN-bus input.
P82C150
Table 1
SYMBOL PIN P2 P3 P4 VSS P5 P6 P7 VDD P8 P9 P10 P11 P12 P13 P14 P15 P16 AVDD REF AVSS RX0 RX1 RST XMOD TX0 TX1 P0/CLK P1 Note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
External reset input (active-HIGH) for internal oscillator mode; pulled to +5 V for external oscillator mode (see Section 11.3). Connected to GND for internal oscillator mode; external reset input (active-LOW) for external oscillator mode (see Section 11.3). Open-drain CAN-bus output: dominant = LOW; recessive = floating. Open-drain CAN-bus output: dominant = HIGH; recessive or at bus mode 2 floating. I/O Port P0, Identifier programming input in internal oscillator mode; clock input in external oscillator mode (see Section 11.3). I/O Port P1; identifier programming input.
1. In this documentation the port pins are referred to by their symbols, not by their pin number. For example P15 means I/O Port 15 at pin 16.
1996 Jun 19
7
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7 7.1 FUNCTIONAL DESCRIPTION I/O functions
P82C150
The P82C150 provides 16 port pins (P15 to P0) which are individually configurable via CAN-bus. Besides the digital I/O functions some of these port pins provide analog I/O functions. 7.1.1 DIGITAL INPUT FUNCTIONS
Analog-to-digital converted digital results are obtained by reading the Analog-to-Digital Conversion (ADC) Register. Analog functions of each port pin are individually controlled by the Analog Configuration Register. Writing the I/O registers is done serially via CAN-bus by Data Frames. The first data byte contains the register address, and the second and third data bytes represent the register contents. If a read only register is addressed, the contents of the second and third data bytes are ignored. It is recommended to set unused port pins to HIGH (100 k resistor to VDD).
Input levels HIGH and LOW on the port pins (P15 to P0) can be read in two ways by the host node: * Polling: a Remote Frame is sent to the P82C150 to be answered by a Data Frame containing the Data Input Register contents. * Event capture: in case of edge-triggered mode, the P82C150 sends the same Data Frame caused by the event of a rising and/or falling edge on the corresponding port pins (see Table 3). 7.1.2 DIGITAL OUTPUT FUNCTIONS
handbook, halfpage
Px
DIx
The Data Output Register is set via a CAN message. Its content is only output when the corresponding bits of the Output Enable Register are set to logic 1s. 7.1.3 ANALOG INPUT/OUTPUT FUNCTIONS
P82C150
MHA068
DOx 3-state buffer OEx
* Up to six multiplexed analog input signals for analog-to-digital conversion or general purpose * Up to two quasi-analog output channels (DPM; Distributed Pulse Modulation) * Two input comparators, for example for window comparator applications * A separate analog-to-digital input comparator with feedback output.
Fig.4 I/O port pins.
1996 Jun 19
8
7.2
Table 2 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB)
I/O register map
1996 Jun 19 I/O registers DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 NE11 NE10 NE9 NE8 NE7 NE6 NE5 NE4 NE3 NE2 NE1 NE0 DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 OE11 OE10 OE9 OE8 OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 0 M3 M2 M1 SW3 SW2 SW1 0 0 0 0 0
15 (MSB)
14
13
ADDRESS 0: DATA INPUT
DI15
DI14
DI13
DI12
Philips Semiconductors
ADDRESS 1: POSITIVE EDGE
PE15
PE14
PE13
PE12
ADDRESS 2: NEGATIVE EDGE
NE15
NE14
NE13
NE12
ADDRESS 3: DATA OUTPUT
DO15
DO14
DO13
DO12
ADDRESS 4: OUTPUT ENABLE
OE15
OE14
OE13
OE12
ADDRESS 5: ANALOG CONFIGURATION
ADC
OC3
OC2
OC1
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
9 DP5 DP4 DP3 DP2 DP1 DP0 0 0 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 AD5 AD4 AD3 AD2 AD1 AD0 0 0
ADDRESS 6: DPM1 0 0 0 0
DP9
DP8
DP7
DP6
ADDRESS 7: DPM2 0 0 0 0
DQ9
DQ8
DQ7
DQ6
ADDRESS 8: ANALOG-TO-DIGITAL CONVERSION (ADC) 0 0 0 0
AD9
AD8
AD7
AD6
Preliminary specification
P82C150
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.2.1 DATA INPUT REGISTER (ADDRESS 0) 7.2.3
P82C150
NEGATIVE EDGE REGISTER (ADDRESS 2)
This read only register contains the states of port pins P15 to P0 which are transmitted on request, or automatically by change of one of the input levels, provided that the respective input is configured to event capture mode (see Table 3). When an edge is detected the port state is loaded into the transmit buffer after the Control Field of the triggered message is sent. Therefore a delay for input settling is provided. If between edge detection and transmission of the data input register another input signal change at the input port occurs, the corresponding data input register bit is overwritten by the current input port value. Additionally the register content is sent automatically after wake-up or bus mode change, once the bit time has been calibrated (part of the `sign-on' message). 7.2.2 POSITIVE EDGE REGISTER (ADDRESS 1)
This write only register contains configuration information per port pin for the event capture facility. The corresponding NE-bit (see Table 3) has to be set to logic 1 to enable capturing of the falling edge. The combination of PE and NE functions is possible. 7.2.4 DATA OUTPUT REGISTER (ADDRESS 3)
This write only register contains the output data for the port pins. The output drivers are bitwise enabled by OE (see Section 7.2.5). New data for the output port register are processed and written to the output ports directly after the corresponding CAN message to the P82C150 is successfully checked and becomes valid. 7.2.5 OUTPUT ENABLE REGISTER (ADDRESS 4)
This write only register contains configuration information per port pin for the event capture facility. The corresponding PE-bit (see Table 3) has to be set to logic 1 to enable capturing of the rising edge.
This write only register controls the output drivers of the port pins. The corresponding Output Enable Register bit has to be set to logic 1 to enable an output driver. If set to logic 0, the corresponding output driver is disabled (floating; see Fig.7).
Table 3 Programming of the I/O registers to event capture on edge or to digital output X = don' t care; n = 0 to 15. REGISTER CONTENTS OF PARTICULAR PORT PIN FUNCTION Digital output Digital input Polling Event capture on edge Rising Falling Rising and Falling 1 0 1 0 1 1 X X X X X X POSITIVE EDGE (BITS PEn) X NEGATIVE EDGE (BITS NEn) X OUTPUT ENABLE (BITS OEn) 1
1996 Jun 19
10
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.2.6 ANALOG CONFIGURATION REGISTER (ADDRESS 5) 7.2.7 DPM1 REGISTER (ADDRESS 6)
P82C150
This read/write register contains the bits ADC, OC3 to OC1, M3 to M1 and SW3 to SW1 (see Fig.7). * ADC bit (analog-to-digital conversion start bit; write only bit). The P82C150 starts an analog-to-digital conversion cycle at ADC = 1 ended with the transmission of a message containing the result. After that, the ADC bit is reset automatically. * OC3 to OC1 bits (comparator output data; read only bits). The bits OC3 to OC1 represent the logical output level of the analog comparators at input port pins P10, P11, P12, P13 and P15. The P82C150 sends back the logical output value of these comparators after having received a Data Frame (see Section 7.3.3) addressing the Analog Configuration Register. The comparator outputs can be monitored at the output port pins P8, P9 and P7. * M3 to M1 bits (multiplexer control bits; write only bits). The logical value of the comparators is monitored on port pins P8, P9 and P7 (see Fig.7) by setting M3 to M1 to logic 1, provided that these pins are configured as outputs (OE = 1). Additionally the register content is sent automatically when the corresponding port bits in the Positive Edge Register and/or Negative Edge Register and the corresponding bits in the Output Enable Register are set. * SW3 to SW1 (analog switch control bits; write only bits). One of the analog switches S1 to S6 can be closed by setting the switch bits to the corresponding value (see Fig.7 and Table 4). Table 4 SW3 0 0 0 0 1 1 1 1 Note 1. Evidently if P14 is driven, it may not be connected to any other driven pin via the internal analog switches (avoid short-circuit!). Analog switch selection by SW3, SW2, SW1. SW2 0 0 1 1 0 0 1 1 SW1 0 1 0 1 0 1 0 1 SWITCH STATE no switch closed (S0); note 1 S1 closed S2 closed S3 closed S4 closed S5 closed S6 closed reserved
This write only register contains data for a quasi-analog output signal on port pin P10, which is generated by Distributed Pulse Modulation (DPM; see Fig.9). The Output Enable bit must be set for this functions (OE10 = 1). The DPM1 output signal is inverted by setting DO10 = 1. The number of output pulses during a DPM period is given by the DPM1 Register value. These pulses have 4 x tCLK length and are distributed over the DPM period. An analog voltage is provided after smoothing the output signal by an external RC combination. 7.2.8 DPM2 REGISTER (ADDRESS 7)
This write only register contains data for a quasi-analog output signal on port pin P4. The function of the DPM2 corresponds to the definition of DPM1. 7.2.9 ANALOG-TO-DIGITAL CONVERSION (ADC) REGISTER (ADDRESS 8)
This read only register contains the result of the analog-to-digital converted level of that I/O pin which was selected by the SW bits. The conversion is started by ADC-bit set to logic 1 (see Section 7.2.6), or by transmitting a Data Frame addressing the ADC Register.
1996 Jun 19
11
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
P82C150
ok, full pagewidth
P16
17
R2 P15 C1 R1 15 P14 M1 DO7 S0 OE7 P7 P6 P5 P8 P9 P13 7 6 5 9 10 14 S1 S2 S3 S4 M2 S5 OE9 S6 DO9 OE8 M3 DO8 SW3 to SW1 16 + - 1/2 V DD 1/4fCLK OC1 ADC REGISTER
P82C150
+ P12 13 - =1 P11 P10 P4 12 11 3 + - OE4 =1 DO4 DPM2 DO10 OE10 DPM1
OC2
OC3
MHA067
Fig.5 Analog configuration of I/O port pins; R1, R2 and C1 are used to implement the analog-to-digital converter.
1996 Jun 19
12
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
P82C150
handbook, full pagewidth
H DPM = 0 L H DPM = 1 L H DPM = 2 L H DPM = 3 L H DPM = 512 L H DPM = 513 L H DPM = 1023 L t DPM = 1024 x 4 t CLK
MHA081
4 t CLK
Distributed Pulse Modulation (DPM) is a special pulse count modulation.
Fig.6 DPM output pulses at DO10(4) = 0; output pulses are inverted at DO10(4) = 1.
1996 Jun 19
13
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.3 CAN functions
P82C150
The P82C150 meets the CAN protocol specification version 2.0 A and B (passive) with restricted bit timing because of the on-chip RC-oscillator and the automatic bit rate detection. In a system with P82C150 nodes there must be at least one conventional crystal-driven CAN controller (host node) which is compatible to the CAN specification V1.2 or later to control P82C150 nodes. Host nodes compatible to CAN specification V1.1 can also be used provided that the P82C150 nodes are powered by a high-accuracy power supply or they are in external oscillator mode (refer to Section 11.3). Each time a P82C150 node receives a Data Frame, it initiates the transmission of a Data Frame containing four bits status information, the register address (previously received) and the current contents of the addressed register (exception: see Section 7.3.3.1). This enables the Table 5 Message types and format TRANSMISSION BY 82C150 yes (DLC = 3; DIR = 1) no yes yes (only as a response)
host node to verify that the addressed register has correctly been written in case of writeable registers, and to read the contents in case of readable registers. 7.3.1 CAN IDENTIFIER
Data and Remote Frames to be processed by the P82C150 are of Standard Format with 11 Identifier bits ID.10 to ID.0. Frames with extended Identifier (CAN specification version 2.0 B) are ignored. The way of identifier programming is based on two facts: * Each P82C150 operates with only two Identifiers distinguished by the LSB (see Tables 5, 6 and 7). The identifier with the higher priority is used for Data Frame reception. An extra Identifier is used for calibration purposes. * There can be maximum sixteen P82C150 circuits in one network.
FRAME Data Frame Remote Frame Error Frame Overload Frame Note
RECEPTION AT 82C150 yes (DLC = 3; DIR = 0; calibration message with DLC = 2 to 8 allowed, see Section 7.3.10) yes (DLC = 3; DIR = 1) yes yes
1. DLC = Data Length Code; DIR = LSB of Identifier (see Section 7.3.1). Table 6 Standard Format Identifier bits ID.10 to ID.0 1 = recessive; 0 = dominant IDENTIFIER ID.10 0 Table 7 BIT ID.8 ID.9 1 ID.8 P3 ID.7 1 ID.6 0 ID.5 P2 ID.4 P1 ID.3 P0 ID.2 1 ID.1 0 ID.0 DIR RTR
Description of the Standard Format Identifier bits SYMBOL P3 DESCRIPTION Programmable identifier bits read from Port pins P3 to P0 during reset. The input levels on P3 to P0, for example set by resistors to VSS or to VDD, are latched in the Identifier latch with the falling edge of the RST input signal. They represent the variable part of the Identifier, while the remaining bits are fixed (mask-programmed), P3 to P0 can be used as I/O ports after reset. DIR = 1 for transmission of Data Frames to the host. It must be set to a logic 1 in Remote Frames and to a logic 0 in Data Frames received from the host. Remote Transmission Request bit. 14
ID.5 to ID.3 P2 to P0
ID.0
DIR RTR
1996 Jun 19
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.3.2 TRANSMISSION OF DATA FRAMES
P82C150
Data Frames transmitted by the P82C150 contain three data bytes (see Fig.7). The first data byte contains the status information and the register address A3 to A0 (see Tables 8 and 9), the other two data bytes contain the content of the addressed I/O Register. After each successful message transmission, the P82C150 delays the transmission of a possibly further pending message for three bit times. The reason is to give other CAN controllers - with a lower identifier priority - the possibility to transmit a message in case of faulty contact at one of the edge-triggered port pins. 7.3.3 RECEPTION OF DATA FRAMES AND REMOTE FRAMES
2. ADC Register: On receiving a Data Frame addressing the ADC Register, the P82C150 starts an analog-to-digital conversion cycle. It automatically returns the result of the conversion (ADC Register) by transmitting a respective Data Frame after finishing the analog-to-digital conversion cycle. 3. At normal operation, the calibration messages are confirmed by returning a dominant bit in the acknowledge slot. There is no particular confirmation message returned by the P82C150. Only after entering the calibrated state (start-up), a Data Frame (`sign-on' message) containing the Data Input Register contents is transmitted indicating to the host node, that the P82C150 is now ready for transmission.
7.3.3.2
Remote Frame
Received Data Frames have the same format as transmitted ones, only the DIR-bit (ID.0) in the Arbitration Field is different. The status bits RSTD, EW, BM1 and BM0 are ignored during reception. The P82C150 confirms each reception of a Data Frame by transmitting a Data Frame containing the (new) contents of the addressed I/O Register.
Received Remote Frames must have the Data Length Code DLC = 3 (Remote Frames with DLC 3 are ignored). It is answered by a Data Frame containing the contents of the Data Input Register.
7.3.3.1
Exceptions to the rule
1. Analog Configuration Register: If a P82C150 receives a Data Frame addressing the Analog Configuration Register and the ADC bit is set to logic 1, it will respond with two messages. The first message returns the contents of the Analog Configuration Register. The control instructions are executed (e.g. next analog input channel selected), and an analog-to-digital conversion cycle is started after a set-up time. After finishing the analog-to-digital conversion cycle, the second message is transmitted containing the result (ADC Register).
1996 Jun 19
15
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
Table 8 Data Frame Byte 1 STATUS RSTD Table 9 EW BM1 BM0 A3 REGISTER ADDRESS A2 A1
P82C150
A0
Description of Data Frame Byte 1 bits DESCRIPTION
SYMBOL Status RSTD EW
It is logic 1 in the first message (`sign-on' message) after the successful detection of the bit rate (bit time calibrated). Logic 1, if the error warning limit (32) is reached. In the "sign-on" message EW is always logic 1. The EW status bit is set when the Receive Error Counter or the Transmit Error Counter have exceeded the Error Warning Limit of 32, also temporarily, since the last successful transmission of a message. Bus mode status bits.
BM1 BM0
Register address A3 to A0 Register address bits.
handbook, full pagewidth
SOF
ARBITRATION FIELD ID10 Identifier 1 P3 1 0 P2 P1 P0 1 0 ID0 DIR RTR
0
0
CONTROL FIELD reserved 0 0 Data Length Code 0 0 1 1 P82C150 status RSTD EW
BYTE 1 register address A3 A2 A1 A0
BM1 BM0
BYTE 2 I/O Register data(15 to 8) X X X X X X X X X X
BYTE 3 I/O Register data(7 to 0) X X X X X X
MHA071
SOF: Start Of Frame. RTR: Remote Transmission Request. P3 to P0: equals programmed identifier bits.
Fig.7 P82C150 Data Frame.
1996 Jun 19
16
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.3.4 CAN-BUS MODES
P82C150
The P82C150 can pass through four CAN-bus modes under certain conditions (see Fig.8). In the bus modes 0 to 2 (see Table 10) the P82C150 is operating with different input comparator configurations. Bus mode 3 is the power reduced Sleep Mode. The bus modes support: * Communication on two balanced wires (differential system) * Communication on one wire in a two-wire differential system * Sleep Mode with wake-up via either a dominant signal on RX0 or RX1 input * Connection of a second transmission medium (redundancy) There are two possibilities for condition 1 to switch to the next mode (see Fig.8): * Overflow of the bit counter when 8192 is reached since the last calibration message * Overflow of the Transmit Error Counter (>255; bus-off limit reached). When the bus mode changes, all I/O Registers are cleared and outputs become floating (OE bits cleared). That means the I/O ports return to a fail-safe state whenever the P82C150 looses connection to its host controller. This is a kind of network watchdog function. The status bits are set to the following values after a bus mode change: * RSTD = 1 * EW = 0 * BMnew = BMold + 1. The programmed Identifier bits remain unchanged. Table 10 Can-bus modes BITS BUS MODE BM1 0 = Differential 1 = One-wire RX1 2 = One-wire RX0 3 = Sleep 0 0 1 1 BM0 0 1 0 1 RECESSIVE RX0 > RX1 RX1 < REF RX0 > REF RX0 > REF and RX1 < REF
After reset the P82C150 changes directly into bus mode 3 (Sleep Mode). During Sleep Mode, the internal RC oscillator is stopped, and all the output drivers are disabled (I/O Register contents cleared). A P82C150 in Sleep Mode can be woken up via CAN-bus lines (dominant level on RX0 or RX1) or by a reset condition.
columns
DIFFERENTIAL MODE Inputs: RX0, RX1 Outputs: TX0, TX1
'0'
Condition 2 Condition 1
end of RESET
SLEEP MODE Inputs: RX0, RX1 Outputs: no
ONE-WIRE RX1 MODE Input: RX1 Outputs: TX0, TX1
'3'
Condition 1
'1'
Condition 1 ONE-WIRE RX0 MODE Input: RX0 Output: TX0
'2'
MHA070
Condition 1: bit counter overflow (>8191) or Transmit Error Counter overflow (>255). Condition 2: dominant bit detected on RX0 and RX1.
Fig.8 CAN-bus modes and switch-over conditions.
RECEPTION LEVEL DOMINANT RX0 < RX1 RX1 > REF RX0 < REF RX0 < REF or RX1 > REF
TRANSMISSION TX1 enabled enabled disabled disabled TX0 enabled enabled enabled disabled
Note 1. Output TX1 is disabled in bus mode 2 to tolerate short-circuit between the CAN-bus wires CAN_H and CAN_L.
1996 Jun 19
17
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.3.5 BIT TIMING
P82C150
The Nominal Bit Time of the P82C150 is subdivided into 10 Time Quanta. The Synchronization Time Segment (SYNC_SEG) and the Propagation Time Segment (PROP_SEG) are each one Time Quantum long. The Phase Buffer Segment 1 (PHASE_SEG1) and the Phase Buffer Segment 2 (PHASE_SEG2) are each four Time Quanta long. The Resynchronization Jump Width (SJW) is four Time Quanta long. The sample point is located at the end of the Phase Buffer Segment 1. The Nominal Bit Time is internally adjusted to Table 11 Bit time subdivision
that bit timing which is provided by the crystal driven host (calibration message). The usable bus length at a given bit rate is reduced in comparison to other CAN controllers with programmable bit timing because the Propagation Time Segment is fixed to 110 length of the Nominal Bit Time. The bit segmentation of the crystal driven host should be programmed like the fixed bit segmentation of the P82C150, e.g. one bit time segment is 110 length of the Nominal Bit Time (refer also to Table 15 for bit time programming).
1 BIT TIME BT1 BT2 BT3 BT4 BT5 BT6 BT7 BT8 BT9 BT10
SYNC_SEG PROP_SEG 7.3.6 CAN-BUS TRANSCEIVER
PHASE_SEG1
PHASE_SEG2 The recessive state and the dominant state are not equivalent and may not be mixed-up. The input comparator is configurable depending on the four CAN-bus modes (see Table 10), supporting battery-powered applications (Sleep Mode) and tolerance against bus wiring failures.
The transceiver of the P82C150 consists of the configurable input comparator and of complementary open-drain driver outputs. The reference voltage REF is an additional output.
7.3.6.1
CAN-bus input comparator (RX0, RX1) 7.3.6.2 CAN-bus output drivers (TX0, TX1)
The output driver function is shown in Table 12. The output driver TX1 is disabled in bus mode 2 to tolerate a short-circuit between the CAN-bus lines in a two-wire differential CAN physical layer.
The input comparator monitors the transient voltage on RX1 and RX0. The result of the input comparator is logic 1 if the voltage levels of the CAN-bus lines are regarded as recessive, and logic 0 if they are regarded as dominant. Table 12 CAN-bus driver output function
DOMINANT CAN OUTPUT TX0 TX1 RECESSIVE MODES 0 AND 1 floating floating LOW HIGH MODE 2 LOW floating
RESET STATE, BUS-OFF AND SLEEP MODE (MODE 3) floating floating
1996 Jun 19
18
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.3.7 TRANSMIT AND RECEIVE LOGIC
P82C150
The transmit and receive logic stores the destuffed bit stream which was received or is about to be transmitted. The incoming Identifier is compared with that of the P82C150. The content of the message is transferred to the port logic in case of matching. At transmission, the message about to be sent is put together: the Identifier, the status information, the register address and the content of the addressed register from the port logic. 7.3.8 BIT STREAM PROCESSOR AND ERROR MANAGEMENT LOGIC
From this time on, the bit time is calibrated and fine-tuned by calibration messages with a special Identifier transmitted by the crystal-controlled host. Only P82C150 nodes being calibrated by calibration messages can transmit messages. The first message is transmitted directly after entering the calibrated state (`sign-on' message). Since the P82C150 is not able to transmit as long as the bit time is not calibrated, it cannot wake-up other CAN nodes via the bus line. Hence to keep the network alive, the calibration message must be transmitted regularly by a crystal-controlled (host) node with a maximum repetition period of 8192 bit (bit length measured by the 82C150). It is recommended to select a repetition period between 3800 and maximum 8000 bit times. 7.3.10 CALIBRATION MESSAGE
The Bit Stream Processor (BSP) is a sequencer to control the data stream between the transmit/receive logic (parallel data) and the on-chip CAN transceiver (serial data). Reception/transmission, bit stuffing/destuffing, arbitration and error detection, according to CAN protocol specification version 2.0 A and B (passive), are performed. Further, automatic re-transmission of corrupted messages is handled by means of continuously comparing the output bit stream with the input bit stream. Moreover, the Bit Stream Processor provides control information to calibrate the internal bit time. The Error Management Logic is responsible for the complete CAN-inherent error management. 7.3.9 OSCILLATOR AND CALIBRATION
The calibration message has to meet the following requirements * Transmitted by a crystal-controlled node (host node) * Identifier: 000 1010 1010 (1 = recessive; 0 = dominant) * RTR bit: 0 * Allowed control field: DLC = 2 to 8 * The first recessive to dominant transition after the control field must be followed by another recessive to dominant transition in a distance of exactly 32 bit (stuff bits included). Example of a suitable calibration message (there are others using different data bytes; see Table 13): * Data length code: 0010 * 1st data byte: 1010 1010 (AAH) * 2nd data byte: 0000 0100 (04H).
The P82C150 contains an on-chip RC-oscillator. The bit time is automatically calibrated by messages being received via CAN-bus. During start-up (after wake-up or reset) any message is used to calibrate the bit time until the calibration is sufficient to receive messages correctly.
Table 13 Example of a suitable calibration message The two important 1/0 transitions are marked by underlines; see note 1. SOF 0 Note 1. I = stuff bit (recessive); the total length is 67 bit from start-of-frame to end-of-intermission. ARBITRATION FIELD 000 1010 1010 0 CONTROL FIELD 000I010 DATA BYTE 1 1010 1010 DATA BYTE 2 0000I 0100 CRC FIELD 000I0 1011 1000 00I0
1996 Jun 19
19
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.4 7.4.1 Initialization IDENTIFIER PROGRAMMING
P82C150
Most of the P82C150 identifier bits are fixed. Four bits are programmable via port pins P3 to P0. All output drivers are disabled at reset, also P3 to P0. Thus the outputs are floating unless the input level is defined by external components to define identifier bits. They are latched at the end of reset, and P3 to P0 can be used as port pins. It is not allowed, according to the CAN protocol specification, that multiple bus nodes transmit the same identifier bit combination. Therefore a P82C150 must have one of the 16 possible identifier bit combinations, one that is not yet occupied. 7.4.2 RESET FUNCTION
After rough calibration the P82C150 can receive any valid CAN message correctly and executes respective commands without giving an acknowledge. With another valid CAN message and additionally with one valid calibration message the P82C150 is fully calibrated and sends its `sign-on' message. As long as the P82C150 is fully calibrated the P82C150 acts as an active CAN node. The P82C150 treats any CAN message (including the calibration message) as a valid message, when these messages are terminated by an error passive frame because of a missing acknowledge. This situation may occur whenever a host node works together with P82C150's and the host node doesn't receive an acknowledge as long as the P82C150's are not fully calibrated.
RST = HIGH disables all output drivers P16 to P0, TX0 and TX1. All I/O Registers are automatically cleared and set to logic 0. The bit time is set greater than 50 s. If a particular clock period is necessary, e.g. for a dedicated DPM output frequency, this can be achieved by feeding an external clock signal into P0. RST and TEST must be permanently HIGH for this special mode. A reset is then performed as usual (RST = HIGH; TEST = LOW). Table 14 Situation after RESET STATUS BITS RSTD = 1 EW = 1 BM1 = 0 BM0 = 0 7.4.3 BIT TIME CALIBRATION IDENTIFIER BITS ID.8 equals P3 ID.5 equals P2 ID.4 equals P1 ID.3 equals P0
7.4.3.1
Sign-on message
This special Data Frame is transmitted once by the P82C150 after entering the calibrated state. It indicates to the host node that the P82C150 is ready for transmission. The sign-on message returns the contents of the Data Input Register, and can be recognized by the host mode by checking the RSTD status bit: * Sign-on message RSTD = 1 * Other Data Frames RSTD = 0 Note that in the sign-on message the EW bit is logic 1. Nevertheless the P82C150 status with the error counters are set to logic 0.
The P82C150 must receive at least three messages to calibrate its bit time after reset or change of bus mode. The first message is used to detect the bit time length (rough calibration) between two consecutive falling edges at the output of the CAN input comparator. Therefore the bit stream should contain a sequence of `1010'.
1996 Jun 19
20
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
7.5 P82C150 operation after RESET or change of bus mode
P82C150
Figure 9 illustrates the calibration procedure of the P82C150 after Power-on-reset or after a bus mode change.
andbook, full pagewidth
end of Power-on-reset
bus mode change e.g. due to missing reception of a calibration message within 8192 bit times
ID bits from P0-P3 latched
I/O registers cleared
P82C150 receives 1st message (any message)
P82C150 is roughly calibrated and has started bus-off recovery sequence (counting 129 blocks of 11 recessive bits)
P82C150 receives 2nd message (any message), acknowledge not required but no active error flag allowed
Rough calibration verified
P82C150 receives calibration message within 8192 bit times after wake-up or bus mode change
P82C150 is fine calibrated and I/O register cleared
P82C150 waits until bus-off recovery sequence finished
P82C150 is on bus and ready to send after bus-of f sequence finished
P82C150 sends 'sign-on' message
Communication with host node possible
MHA080
Fig.9 SLIO operation flow after reset and bus mode change.
1996 Jun 19
21
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IREF IO PARAMETER supply voltage on VDD pin DC input voltage on any pin (RX0, RX1, TX0, TX1 excluded) RX1 and RX0 input current reference output current port output current at port enabled (pins P0 to P15) port output current at analog switch enabled (OE-bits = 0; pins P5 to P9, P13, P14) TX0 and TX1 output current POtot Tamb Tstg Ptot total power dissipation (port outputs together) operating ambient temperature range: storage temperature range total power dissipation MIN. -0.5 -0.5 - - - - - - -40 -65 -
P82C150
MAX. +6.5 VDD + 0.5 2 2 5 7.5 30 200 +125 +150 1 V V
UNIT
mA mA mA mA mA mW C C W
1996 Jun 19
22
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
P82C150
9 DC CHARACTERISTICS VDD = 5 V 4%; VSS = 0 V; Tamb = -40 to +85 C and Tamb = -40 to +125 C; unless otherwise specified. SYMBOL Supply VDD IDD IDD(SM) supply voltage operating supply current supply current Sleep mode note 1 VRST = VDD; all port inputs connected via 1 M to GND Ports P15, P13 and P11 connected to VDD; Ports P12 and P10 connected to VSS; all other port inputs connected via 1 M to GND 100 8 - - VDD - 0.1 VDD - 1.0 0.5AVDD - 0.25 - 0.7VDD note 2 0.45 V < VI < VDD - 0.45 V IOL = 4mA (sink) IOH = -4mA (source) 1.5 V < VI < (AVDD - 1.5 V); note 2 - VDD - 1.0 20 0.5 0.5AVDD + 0.25 0.2VDD - - 10 4.8 - 5.2 22 1 V mA mA PARAMETER CONDITIONS MIN. MAX. UNIT
CAN Input comparators RX0 and RX1 VDIF VHYST II VOLT VOHT differential input voltage input voltage hysteresis input current 0.3AVDD < VI < 0.7AVDD; note 2 0.45 V < VI < VDD - 0.45 V IOLT = 1.5 mA IOLT = 10 mA IOHT = -1.5 mA IOHT = -10 mA IO < 75 A - 60 400 mV mV nA
CAN output driver TX0 and TX1; port pins P0 to P16 unloaded TX0 output voltage LOW; note 3 TX1 output voltage HIGH; note 4 0.1 1.0 - V V V V
Reference voltage REF VREF VIL VIH VHYST IIL1 VOL VOH VDIF1 reference output voltage V
Control inputs RST, XMOD and digital port inputs P0/CLK, P1 to P15 input voltage LOW input voltage HIGH input voltage hysteresis input leakage current V V V A
Digital port outputs P0/CLK, P1 to P16; OE bits set output voltage LOW output voltage HIGH 1.0 - - V V
OC2 comparator P12, P13 and OC3 comparator P10, P11 differential input voltage mV
1996 Jun 19
23
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
SYMBOL PARAMETER CONDITIONS 1.5 V < VI < (AVDD - 1.5 V); note 2 0.45 V < VI < VDD - 0.45 V note 2 MIN.
P82C150
MAX.
UNIT
OC1 comparator input P15 Vi sw input switch-over voltage lower threshold upper threshold ILI2 CIA RON input leakage current analog input capacitance 0.5VDD - 0.02 - - - 0.5VDD + 0.02 400 20 V V nA pF
Analog switches; ION = 4 mA On resistance between P5 to P9, P13 and P14; note 2 20 200
Notes to the DC characteristics: 1. Alteration of VDD between two calibration messages should not exceed 0.2 V to avoid failures during CAN message transfer. If CAN devices according to CAN specification V1.0 or V1.1 (like the 82C200 V0 or V1) are in the same network with the 82C150, then this alteration of VDD should be limited to 0.1V for the 82C150. 2. These values are characterized but not 100% production tested. 3. The TX0 output pin is an open drain pull-down driver (no pull-up driver included). 4. The TX1 output pin is an open drain pull-up driver (no pull-down driver included). 10 AC CHARACTERISTICS VDD = 5 V 4%; VSS = 0 V; CL = 100 pF (output pins); Tamb = -40 to +85 C and Tamb = -40 to +125 C; unless otherwise specified. SYMBOL fCLK_INT tbit tRST1 tRST2 thold td trep tcyc tinit tresp tDPM Notes 1. Other bit time values are possible with the external oscillator mode (refer to Chapter 11.3). 2. These values are characterized but not 100% production tested. PARAMETER system clock frequency on-chip bit time on CAN-bus min. RST pulse width after power on min. RST pulse width during operation ID hold time after end of reset total signal delay of CAN input comparator and CAN output driver max. time without recalibration message CONDITIONS internal oscillator note 1 note 2 note 2 note 2 0.3AVDD < VI < 0.7AVDD; note 2 MIN. 4 8 150 1 100 - - MAX. 10 50 - - - 100 8000 UNIT MHz s ms s ns ns bit
Analog-to-digital comparator input P15 analog-to-digital conversion cycle time initialization time of analog-to-digital conversion VDIF1 = 100 mV; note 2 0.4 0.4 0.4 1.1 2.1 ms ms s
OC2 comparator P12, P13 and OC3 comparator P10, P11 response time 1
DPM1 and DPM2 outputs repetition time of DPM cycle 1.1 ms
1996 Jun 19
24
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
11 APPLICATION INFORMATION 11.1 Maximum bus length 11.1.1 ASSUMPTIONS
P82C150
The bit timing parameters refer to using a P8xCE598 or P8xC592 microcontroller with on-chip CAN interface as a host node (see Fig.20).
* The total in/out delay of external transceiver circuit is less than 180 ns (e.g. PCA82C250 CAN transceiver; see Fig.20). * The propagation delay on the transmission medium is 5.0 ns/m.
Table 15 Maximum bus length for CAN-bus systems with P82C150 nodes. BIT RATE (kbit/s) 125 100 50 20 Notes 1. tprop is the maximum propagation delay between two CAN-bus nodes (delays of on- and off-chip transceiver circuits included). 2. BTR0 and BTR1 (hex values) are particular configuration registers referring to bit timing. 11.2 Start up sequence
handbook, halfpage
tprop(1) (s) 0.8 1 2 5
INDICATION FOR MAXIMUM BUS LENGTH (m) 25 45 145 445
BIT TIMING (P8xCE598/P8xC592) fCLK (MHz) 15 16 16 16 BTR0(2) C5H C7H CFH E7H BTR1(2) 34H 34H 34H 34H
The following start-up sequence, illustrated by Figures 10 and 11, shows a simple example how P82C150 nodes can be controlled from a host node. This application example works with different system configurations: * One conventional crystal-controlled CAN node and one or more P82C150 nodes. * More than one conventional crystal-controlled CAN node and one or more P82C150 nodes.
Power-on
Initialization of host node's CAN controller
Wait until all P82C150 nodes are assumed to have finished Power-on-reset
Start-up bit time calibration procedure (1)
Periodic calibration (transmit calibration message with a repetition period of maximum 8000 bit times)
MHA077
(1) See Fig.11.
Fig.10 General start-up procedure for CAN-bus systems with P82C150 nodes.
1996 Jun 19
25
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
P82C150
handbook, full pagewidth
Load calibration message into transmit buf fer
j := 18
if 'Transmit Status' = 0(1)
else
then Set bit 'Transmission Request' (CMR.0) in Command Register '0'
if 'Transmit Status' = 1(1)
else
then Set bit 'Abort Transmission' (CMR.1) in Command Register
j : = j -1
else
if j = 0 then
Wait for reception of sign-on message from P82C150 nodes
from now onwards transmit calibration message periodically with a recommended repetition period between 3800 and 8000 bit times
MHA079
(1) Bit SR.5 in Status Register.
Fig.11 P82C150 start-up bit time calibration procedure for host node (P8xC592, P8xCE598 or P82C200).
1996 Jun 19
26
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
11.3 External oscillator mode
+5 V
P82C150
In this mode the P82C150 operates with an external clock instead with the on-chip RC-oscillator. Figure 14 shows the application with an external clock. In this mode the P82C150 can achieve bit rates below 20 kbit/s and above 125 kbit/s. The DPM pulse width is 4 x tCLK of the external clock. The corresponding CAN identifier bit at Port P0 is set to a logic 0. Therefore only eight P82C150 based CAN nodes operate within the same network in external oscillator mode. 11.3.1 NOTE
digital input
P82C150
P0 to P15
MHA072
Fig.12 Example for digital input application.
The external oscillator mode is not the normal operation mode. 11.4 Using digital I/O port functions
P82C150
digital output P0 to P15
Figures 12 and 13, show the principle application for digital input and output. 11.5 Using DPM
The simplest way to generate an analog voltage using the P82C150 is to apply an external low pass filter at one of the DPM (Distributed Pulse Modulation) outputs. The simplest implementation concept is a RC-filter of the first order (refer to Fig.15). Regarding the selection of the time constant (edge frequency) of this filter, a trade-off between minimizing of the ripple voltage for maximum accuracy and minimum of the settling time has to be considered.
MHA073
Fig.13 Example for digital output application.
V
handbook, halfpage
V
clock
P82C150
P0/CLK analog output XMOD t t DPM1(2) P10(P4)
reset +5 V
P82C150
RST
MHA074 MHA078
If the output is loaded by a resistive load, this will decrease the accuracy due to the voltage drop across the series resistor. In these cases a low value for the series resistor should be chosen. The repetition time of one DPM cycle can be derived from: 4096 t CYC = -----------f OSC
Fig.14 P82C150 in external oscillator mode.
Fig.15 Example for DPM application.
1996 Jun 19
27
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
11.6 Using ADC 11.7
P82C150
Using analog input port functions
The application in Fig.16 can be used for analog-to-digital conversion for only one analog input signal. The evaluation of ADC were done with the values R1 = R2 = 100 k and C = 3.3 nF; under these conditions the ADC may reach an accuracy of 7 to 8 bit (depends on application). The external components should be connected close to the port pins P15 and P16 with short wiring to avoid disturbances at the analog input port pin P15. Using the on-chip multiplex function the P82C150 provides up to six input port pins to convert analog input signals to digital values (see Fig.17). The period for one ADC cycle is identical to the length of one DPM cycle.
Figure 18 shows the wide range of analog input applications: * Comparison of two analog input signals. * Comparison of one analog input signal against a fixed threshold. * Window comparator including monitoring the comparator outputs at the port pins P8 and P9; additional automatically generated messages, when the corresponding port bits in the Negative Edge and/or Positive Edge register are set. * Local control two-step system.
handbook, halfpage
P15
P82C150
handbook, halfpage
P16 one analog input signal for A/D conversion R2 P15 C R1
P16 feedback analog signal P14
P82C150
V P5 t V
MHA076
SW3 to SW1
P6 t
MHA075
Fig.16 ADC implementation.
Fig.17 Two multiplexed analog input signals switched for analog-to-digital conversion (maximum 6 signals; see Fig.5).
1996 Jun 19
28
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
P82C150
dbook, full pagewidth
V
P82C150
comparison between two analog input signals t V P11 (P13) OC3 (OC2) P10 (P12)
t V message transmission when analog input signal exceeds threshold voltage +5 V
P82C150
t threshold P11 (P13) P10 (P12) M3 (M2) comparator OE8 (OE9) P8 (P9) DI8 (DI9) DO8 (DO9)
output enabled and edge-triggered mode (PE and/or NE set) message transmission when analog input signal exceeds upper respectively lower threshold voltage (window comparator) +5 V
P82C150
upper threshold P11 P10 DO8 M3 comparators sensor signal lower threshold P13 P12 DO9 M2 OE9 P9 DI9 output enabled and edge-triggered mode (PE and/or NE set) output enabled and edge-triggered mode (PE and/or NE set) DI8 OE8
V
t
V
V
t P8
t V local two-step control system +5 V V sensor signal threshold
P82C150
P11 (P13) DO8 (DO9) P10 (P12) M3 (M2) comparator OE8 (OE9)
t
t
to actuator
P8 (P9) output enabled
DI8 (DI9)
MHA082
Fig.18 Examples of comparator applications.
1996 Jun 19
29
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
P82C150
handbook, full pagewidth
V bat
V bat
on/off control
LOAD
linear control with status feedback
LOAD
angle measurement
D
S
D BUK105-50S P F I
S KM110BH/21-90 VS Vo GND
BUK101-50GS I
+5 V 10 k +5 V V
DD
+5 V
PV (digital out) RST
Pz Py Px (DPM) (digital out) (digital in)
Pw (analog in) V
SS
P82C150
REF RX1 TX0 TX1
RX0
MHA083
Fig.19 Examples of TOPFET applications with P82C150.
1996 Jun 19
30
11.8
Preliminary specification
P82C150
Fig.20 P82C150 system application using CAN transceiver PCA82C250 (ISO/DIS 11898 standard).
handbook, full pagewidth
1996 Jun 19
motor lamp digital sensor analog
Philips Semiconductors
M
CAN-bus system applications
TOPFET
(1) TOPFET
XTAL1
P8xC592 / P8xCE598 CAN-CONTROLLER
P82C150
Px,y TX0 560 RX0 TX1 3.6 k RX1 6.8 k
XTAL2 CTX0 CRX0 CRX1
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
Rext = 0
+5 V
+5 V
31
RxD Rs Vref TxD RxD
TxD
Vref
Rs
PCA82C250
CANL CANH
PCA82C250
CANL
CANH
124
CAN BUS LINE
MHA069
124
(1) TOPFET = temperature and Overload-Protected Field-Effect-Transistor
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
12 PACKAGE OUTLINE SO28: plastic small outline package; 28 leads; body width 7.5 mm
P82C150
SOT136-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013AE EIAJ EUROPEAN PROJECTION A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.42 0.39 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
8o 0o
ISSUE DATE 91-08-13 95-01-24
1996 Jun 19
32
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
13 SOLDERING 13.1 Introduction
P82C150
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these cases reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 13.2 Reflow soldering
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Repairing soldered joints
Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 13.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at between 270 and 320 C
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end.
1996 Jun 19
33
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
14 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
P82C150
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Jun 19
34
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with digital and analog port functions
NOTES
P82C150
1996 Jun 19
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 805 4455, Fax. +61 2 805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 708 296 8556 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 615 800, Fax. +358 615 80920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 52 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. +30 1 4894 339/911, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 648 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 83749, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE June 20, 1996 SCA49
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
617021/1200/02/pp36 Date of release: 1996 Jun 19 Document order number: 9397 750 00918

▲Up To Search▲

Price & Availability of P82C150AHT

	To Download P82C150AHT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .